问题描述:
画出与下列实体描述所对应的元件符号;并画出与结构体对应的原理图.
ENTITY adder IS
PORT(a,b:IN STD_LOGIC;
s,co:OUT STD_LOGIC);
END adder;
ARCHITECTURE behave OF adder IS
COMPONENT and2 is
PORT(a,b:IN STD_LOGIC;
c:OUT STD_LOGIC);
END COMPONENT;
COMPONENT xor is
PORT(a,b:IN STD_LOGIC;
c:OUT STD_LOGIC);
END COMPONENT;
BEGIN
U1:and2 PORT MAP( a,b,co);
U2:xor PORT MAP( a,b,s);
END;
ENTITY adder IS
PORT(a,b:IN STD_LOGIC;
s,co:OUT STD_LOGIC);
END adder;
ARCHITECTURE behave OF adder IS
COMPONENT and2 is
PORT(a,b:IN STD_LOGIC;
c:OUT STD_LOGIC);
END COMPONENT;
COMPONENT xor is
PORT(a,b:IN STD_LOGIC;
c:OUT STD_LOGIC);
END COMPONENT;
BEGIN
U1:and2 PORT MAP( a,b,co);
U2:xor PORT MAP( a,b,s);
END;
问题解答:
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