问题描述：
VHDL问题：can't determine definition of operator ""/""--found 0 possible
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity frequency is
port(clk:in std_logic;
frenow:out std_logic_vector(32 downto 0));
end frequency;
architecture BEHAVIORAL of frequency is
begin
process(clk)
variable e:real;
begin
e:=85899*50000000/4294967296;
frenow
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity frequency is
port(clk:in std_logic;
frenow:out std_logic_vector(32 downto 0));
end frequency;
architecture BEHAVIORAL of frequency is
begin
process(clk)
variable e:real;
begin
e:=85899*50000000/4294967296;
frenow
问题解答：
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