问题描述：
英语翻译
The FPGA and SerDes we use cost about $40,a about third of the cost for the cheapest Xilinx Virtex-II Pro series FPGA necessary for implementing a system as in [11].Using this hardware we currently achieve event rates that are about three to four times faster than in [11].
Such a Serializer-Deserializer locally receives data on a parallel bus and then sends it over a serial output at a multiple of the parallel interface speed and vice versa for the serial receive path.The parallel interface is usually used for on-board,the serial for off-board communication.
•\x05In the approach described in [11],the receiver simply drops events if it is not ready to receive them.We implemented a flow-control scheme that ensures that all events reach its destination.In case the receiver is currently unable to receive an event because it does not have the necessary receive buffer space available,it can tell the sender to stop until space is available.
•\x05The FPGA package type chosen allow for in-house assembly and repair as opposed to the ball-grid-array package used in
[11].
1)\x05SerDes - TI TLK2501 / TLK3101:The SerDes we can use on our system is either the TLK2501 or the TLK3101 from Texas
Instruments.The TLK2501 supports up to 2.5Gbit/s,the TLK3101
supports up to 3.125Gbit/s,and has on-chip termination resistors.As terminating the differential traces correctly is not a trivial layout task,it is easier to achieve working PCB layouts with the TLK3101.Our system both supports the TLK2501 and the TLK3101 as an assembly option.We alsosuccessfully achieved mixed setups where TLK2501 and TLK3101 are communicating with each other at 2.5Gbit/s.
On the parallel side of the SerDes these chips have a 16bit transmit and a 16bit receive bus.They use 8bit/10bit coding and are also otherwise very similar to the Rocket IOs used in [11].With the 16bit word length and the 8bit/10bit coding the SerDes parallel interfaces run at 1/20 of the serial speed.
2)\x05Cables & Connector Pin-Out:We are using Serial ATA con¬nectors and cables to create Serial AER connections between our boards in multi-chip experimental setups.The connectors have seven pins,two differential pairs and three ground pins.With a SATA cable connecting boards A and B,we use the first differential pair of the cable to transmit serial AER data from the SerDes on A to the SerDes on B.The second differential pair is used to feed back a flow-control.
signal from the FPGA on B to the FPGA on A.
On the connector pins 2/3 are SerialAER+/-,pins 5/6 are FlowControl+/-.The remaining pins are the shielding,which we simply left unconnected on both sides,thus having a floating shield.
3)\x05AC Coupling:We decided to used AC coupled instead of the simpler DC coupled serial links.With AC coupled links there is no common ground reference over all the boards in a system.This eliminates board-to-board ground-bounce problems,and also reduces line frequency injection.
The FPGA and SerDes we use cost about $40,a about third of the cost for the cheapest Xilinx Virtex-II Pro series FPGA necessary for implementing a system as in [11].Using this hardware we currently achieve event rates that are about three to four times faster than in [11].
Such a Serializer-Deserializer locally receives data on a parallel bus and then sends it over a serial output at a multiple of the parallel interface speed and vice versa for the serial receive path.The parallel interface is usually used for on-board,the serial for off-board communication.
•\x05In the approach described in [11],the receiver simply drops events if it is not ready to receive them.We implemented a flow-control scheme that ensures that all events reach its destination.In case the receiver is currently unable to receive an event because it does not have the necessary receive buffer space available,it can tell the sender to stop until space is available.
•\x05The FPGA package type chosen allow for in-house assembly and repair as opposed to the ball-grid-array package used in
[11].
1)\x05SerDes - TI TLK2501 / TLK3101:The SerDes we can use on our system is either the TLK2501 or the TLK3101 from Texas
Instruments.The TLK2501 supports up to 2.5Gbit/s,the TLK3101
supports up to 3.125Gbit/s,and has on-chip termination resistors.As terminating the differential traces correctly is not a trivial layout task,it is easier to achieve working PCB layouts with the TLK3101.Our system both supports the TLK2501 and the TLK3101 as an assembly option.We alsosuccessfully achieved mixed setups where TLK2501 and TLK3101 are communicating with each other at 2.5Gbit/s.
On the parallel side of the SerDes these chips have a 16bit transmit and a 16bit receive bus.They use 8bit/10bit coding and are also otherwise very similar to the Rocket IOs used in [11].With the 16bit word length and the 8bit/10bit coding the SerDes parallel interfaces run at 1/20 of the serial speed.
2)\x05Cables & Connector Pin-Out:We are using Serial ATA con¬nectors and cables to create Serial AER connections between our boards in multi-chip experimental setups.The connectors have seven pins,two differential pairs and three ground pins.With a SATA cable connecting boards A and B,we use the first differential pair of the cable to transmit serial AER data from the SerDes on A to the SerDes on B.The second differential pair is used to feed back a flow-control.
signal from the FPGA on B to the FPGA on A.
On the connector pins 2/3 are SerialAER+/-,pins 5/6 are FlowControl+/-.The remaining pins are the shielding,which we simply left unconnected on both sides,thus having a floating shield.
3)\x05AC Coupling:We decided to used AC coupled instead of the simpler DC coupled serial links.With AC coupled links there is no common ground reference over all the boards in a system.This eliminates board-to-board ground-bounce problems,and also reduces line frequency injection.
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