Error:Top-level design entity "Verilog1" is undefined

Most likely you named the project something different than your top-level entity/module/filename. (Type depends on source, where entity=VHDL, module=Verilog, and filename.bdf=schematic). To tell Quartus that the top-level entity/module/etc. is something else, go to Assignments -> Settings -> General and type the name there.