问题描述:
英语翻译
These multiplexing strategies are very efficient because only the addresses of active elements are transmitted (as opposed to conventional scanning techniques that allocate the same bandwidth for all the pixels,independent of their activity).The source addressevents (AEs) being transmitted on the digital bus can be translated,converted or remapped to multiple destinations using conventional logic and memory elements.AER infrastructures therefore allow us to construct large multi-chip networks with arbitrary connectivity,and to seamlessly reconfigure the network topology.
As the trend to develop complex AER multi-chip experimental setups is increasing,there is a strong need for robust and reliable AER communication infrastructures,that can be easily interfaced to workstations or laptops during a prototyping phase,and that can be embedded into compact and low-cost systems in the application phase.
Existing AER Infrastructure and Approaches
Conventional approaches that use general purpose hardware in multi-chip AER systems involve logic-analyzers or general purpose digital data acquisition systems,but these approaches usually suffer drawbacks regarding asynchronous communication or on-line analysis of the acquired data [3].This requires the design of special purpose hardware for building and debugging multi-chip AER systems.
For example a generic AER interfacing solution implemented using special purpose hardware is the PCI-AER board [3].It consists of a custom made PCI card and a daughter board which are connected by a ribbon cable.The daughter board has parallel AER interface connectors and supports up to four input channels and four output channels.The PCI board consists of multiple FPGAs,FIFOs,SRAM and a PCI interface controller chip.The PCI board can monitor 备注0 incoming AE streams and then send the timestamped AEs via PCI to a program running on the computer.It can also do the reverse:sequence 备注0 timestamped data provided to it over the PCI bus out on any or all of the output channels.The FPGAs on the PCI-AER board also implement a one to many mapper that can be reconfigured via the PCI interface.
Recent boards for interfacing AER to PC were also implemented using USB instead of PCI,e.g.[10].
Similarly,recent serial AER communication schemes were proposed in [11].
Other groups building multi-chip AER systems tend not to use generic AER infrastructure,but build special purpose PCBs on a perproject basis e.g.[2],[12],or analogous solutions that are not as flexible,or powerful,as the system described here.
Here we propose a general purpose serial AER infrastructure that can be reused in multiple projects or experimental setups.
These multiplexing strategies are very efficient because only the addresses of active elements are transmitted (as opposed to conventional scanning techniques that allocate the same bandwidth for all the pixels,independent of their activity).The source addressevents (AEs) being transmitted on the digital bus can be translated,converted or remapped to multiple destinations using conventional logic and memory elements.AER infrastructures therefore allow us to construct large multi-chip networks with arbitrary connectivity,and to seamlessly reconfigure the network topology.
As the trend to develop complex AER multi-chip experimental setups is increasing,there is a strong need for robust and reliable AER communication infrastructures,that can be easily interfaced to workstations or laptops during a prototyping phase,and that can be embedded into compact and low-cost systems in the application phase.
Existing AER Infrastructure and Approaches
Conventional approaches that use general purpose hardware in multi-chip AER systems involve logic-analyzers or general purpose digital data acquisition systems,but these approaches usually suffer drawbacks regarding asynchronous communication or on-line analysis of the acquired data [3].This requires the design of special purpose hardware for building and debugging multi-chip AER systems.
For example a generic AER interfacing solution implemented using special purpose hardware is the PCI-AER board [3].It consists of a custom made PCI card and a daughter board which are connected by a ribbon cable.The daughter board has parallel AER interface connectors and supports up to four input channels and four output channels.The PCI board consists of multiple FPGAs,FIFOs,SRAM and a PCI interface controller chip.The PCI board can monitor 备注0 incoming AE streams and then send the timestamped AEs via PCI to a program running on the computer.It can also do the reverse:sequence 备注0 timestamped data provided to it over the PCI bus out on any or all of the output channels.The FPGAs on the PCI-AER board also implement a one to many mapper that can be reconfigured via the PCI interface.
Recent boards for interfacing AER to PC were also implemented using USB instead of PCI,e.g.[10].
Similarly,recent serial AER communication schemes were proposed in [11].
Other groups building multi-chip AER systems tend not to use generic AER infrastructure,but build special purpose PCBs on a perproject basis e.g.[2],[12],or analogous solutions that are not as flexible,or powerful,as the system described here.
Here we propose a general purpose serial AER infrastructure that can be reused in multiple projects or experimental setups.
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